philips semiconductors pck111 low voltage 1:10 differential ecl/pecl/hstl clock driver product data supersedes data of 2003 dec 03 2004 apr 23 integrated circuits
philips semiconductors product data pck111 low voltage 1:10 differential ecl/pecl/hstl clock driver 2 2004 apr 23 features ? 85 ps part-to-part skew typical ? 20 ps output-to-output skew typical ? differential design ? v bb output ? low voltage v ee range of 2.25 v to 3.8 v for ecl ? low voltage v cc range of +2.375 v to +3.8 v for pecl ? 75 k w input pull-down resistors ? ecl/pecl outputs ? form, fit, and function compatible with mc100ep111 description the pck111 is a low skew 1-to-10 differential driver, designed with clock distribution in mind. it accepts two clock sources into an input multiplexer. the pecl input signals can be either differential or single-ended if the v bb output is used. the selected signal is fanned out to 10 identical differential outputs. the pck111 is specifically designed, modeled and produced with low skew as the key goal. optimal design and layout serve to minimize gate-to-gate skew within a device, and empirical modeling is used to determine process control limits that ensure consistent t pd distributions from lot to lot. the net result is a dependable, guaranteed low skew device. to ensure that the tight skew specification is met, it is necessary that both sides of the differential output are terminated into 50 w , even if only one side is being used. in most applications, all ten differential pairs will be used, and therefore terminated. in the case where fewer than ten pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side, in order to maintain minimum skew. failure to do this will result in small degradations of propagation delay (on the order of 1020 ps) of the output(s) being used, which, while not being catastrophic to most designs, will mean a loss of skew margin. the pck111 can be used for high performance clock distribution in +3.3 v or +2.5 v systems. desi gners can take advantage of the pck111's performance to distribute low skew clocks across the backplane or the board. in a pecl environment, series or thevenin line terminations are typically used as they require no additional power supplies. the pck111 may be driven single-endedly utilizing the v bb bias output with the clk0 input. if a single-ended signal is to be used, the v bb pin should be connected to the clk0 input and bypassed to ground via a 0.01 m f capacitor. the v bb output can only source/sink 0.2 ma, therefore, it should be used as a switching reference for the pck111 only. part-to-part skew specifications are not guaranteed when driving the pck111 single-endedly. pinning pin configurations v bb 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 q3 q3 q4 q4 q5 q5 q6 q6 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 pck111bd sw00907 v q9 q9 q8 q8 q7 q7 clk_sel clk0 clk0 clk1 clk1 q0 q0 q1 q1 q2 q2 v ee v cc cco v cco v cco v cco figure 1. lqfp32 pin configuration pck111bs (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 v cc v cco clk_sel clk0 clk0 clk1 clk1 v bb v ee q9 q9 q8 q8 q7 q7 v cco q3 q3 q4 q4 q5 q5 q6 q6 v cco v cco q0 q0 q1 q1 q2 q2 sw02236 figure 2. hvqfn32 pin configuration ordering information type n mber package temperature type n u mber name description version p range pck111bd lqfp32 plastic low profile quad flat package; 32 leads; body 7 7 1.4 mm sot358-1 40 c to +85 c pck111bs hvqfn32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 5 0.85 mm sot617-1 40 c to +85 c
philips semiconductors product data pck111 low voltage 1:10 differential ecl/pecl/hstl clock driver 2004 apr 23 3 pin description symbol pin description v cc 1 supply voltage clk_sel 2 active cmos clock select input clk0, clk0 3, 4 differential ecl/pecl/hstl input pair v bb 5 reference voltage output clk1, clk1 6, 7 differential ecl/pecl/hstl input pair v ee 8 ground v cco 9, 16, 25, 32 output drive power supply voltage q0q9 31, 29, 27, 24, 22, 20, 18, 15, 13, 11 differential pecl outputs q0 q9 30, 28, 26, 23, 21, 19, 17, 14, 12, 10 differential pecl outputs logic symbol sw00908 10 q0:9 q0:9 clk0 clk0 clk1 clk1 1 0 clk_sel v bb figure 3. logic symbol function table clk_sel active input 0 clk0, clk0 1 clk1, clk1 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied. symbol parameter limits unit v cc supply voltage 0.5 to +4.6 v esdhbm electrostatic discharge (human body model; 1.5 k w , 100 pf) >1.75 kv esdmm electrostatic discharge (machine model; 0 k w , 200 pf) >200 v esdcdm electrostatic discharge (charge device model) >1000 v recommended operating conditions symbol parameter conditions min max unit v cc supply voltage 2.25 3.8 v v ir receiver input voltage v ee v cc v v diff input differential voltage 1 v (clkinn) v (clkin) e 1.00 v t amb operating ambient temperature range in free air 40 +85 c note: 1. to idle an unused differential clock input, connect one input terminal (e.g. clk1) to v bb and leave its complimentary input terminal (e.g. clk1 ) open-circuit, in which case clk1 will default low by its internal pull-down reistor. inputs should not be shorted to ground or v cc .
philips semiconductors product data pck111 low voltage 1:10 differential ecl/pecl/hstl clock driver 2004 apr 23 4 dc electrical characteristics v cc = 0 v, v ee = 2.25 to 3.80 v symbol parameter condition 40 c min 40 c max 25 c min 25 c max 85 c min 85 c max unit i ee internal supply current absolute value of current 45 85 60 95 65 105 ma i cc output and internal supply current all outputs terminated 50 w to v cc = 2.0 v 270 360 290 380 300 380 ma i in input current includes pullup/pulldown resistors e 150 e 150 e 150 m a v bb internal bias voltage 1.38 1.23 1.38 1.23 1.38 1.23 v v ih in p ut high voltage single ended 1.165 0.880 1.165 0.880 1.165 0.880 v v ih in ut high voltage clk_sel 0.2v ee v cc 0.2v ee v cc 0.2v ee v cc v v il in p ut low voltage single ended 1.810 1.475 1.810 1.475 1.810 1.475 v v il in ut low voltage clk_sel v ee 0.8v ee v ee 0.8v ee v ee 0.8v ee v v pp input amplitude difference of input = v ih v il (note 1) 0.5 1.3 0.5 1.3 0.5 1.3 v v cmr common mode voltage cross point of input = average (v ih , v il ) v ee + 1.0 0.3 v ee + 1.0 0.3 v ee + 1.0 0.3 v v oh output high voltage i oh = 30 ma 1.3 0.95 e e 1.2 0.90 v v ol output low voltage i ol = 5 ma 1.85 1.4 e e 1.90 1.5 v v outpp differential output swing 350 e e e 500 e mv note: 1. v pp minimum and maximum required to maintain ac specifications. actual device function will tolerate minimum v pp of 100 mv. dc electrical characteristics v cc = v cco = 2.25 to 3.80 v, v ee = 0 v symbol parameter condition 40 c min 40 c max 25 c min 25 c max 85 c min 85 c max unit i ee internal supply current absolute value of current 45 85 60 95 65 105 ma i cc output and internal supply current all outputs terminated 50 w to v cc = 2.0 v 270 360 290 380 300 380 ma i in input current includes pullup/pulldown resistors e 150 e 150 e 150 m a v bb internal bias voltage v cc 1.38 v cc 1.23 v cc 1.38 v cc 1.23 v cc 1.38 v cc 1.23 v v ih input high voltage single ended v cc 1.165 v cc 0.880 v cc 1.165 v cc 0.880 v cc 1.165 v cc 0.880 v ih g clk_sel 0.8v cc v cc 0.8v cc v cc 0.8v cc v cc v v il input low voltage single ended v cc 1.810 v cc 1.475 v cc 1.810 v cc 1.475 v cc 1.810 v cc 1.475 v il g clk_sel v ee 0.2v cc v ee 0.2v cc v ee 0.2v cc v v pp input amplitude difference of input = v ih v il (note 1) 0.5 1.3 0.5 1.3 0.5 1.3 v v cmr common mode voltage cross point of input = average (v ih , v il ) 1.0 v cc 0.3 1.0 v cc 0.3 1.0 v cc 0.3 v v ihcmr input high voltage (hstl) 1.2 v cc 1.2 v cc 1.2 v cc v v x input crossover voltage (hstl) cross point of input = average (v ih , v il ) 0.68 0.9 0.68 0.9 0.68 0.9 v v oh output high voltage i oh = 30 ma v cc 1.30 v cc 0.95 e e v cc 1.20 v cc 0.90 v v ol output low voltage i ol = 5 ma v cc 1.85 v cc 1.40 e e v cc 1.90 v cc 1.50 v v outpp differential output swing 350 e e e 500 e mv note: 1. v pp minimum and maximum required to maintain ac specifications. actual device function will tolerate minimum v pp of 100 mv.
philips semiconductors product data pck111 low voltage 1:10 differential ecl/pecl/hstl clock driver 2004 apr 23 5 ac electrical characteristics v cc = 2.25 v to 3.80 v, v ee = 0 v, or v cc = 0 v, v ee = 2.25 v to 3.80 v symbol parameter condition 40 c min 40 c max 25 c min 25 c max 85 c min 85 c max unit t pd differential propagation delay nominal (single input condition) v pp = 0.650 v, v cmr = v cc 0.800 v (note 1) 350 500 380 530 450 590 ps t skew part-to-part skew note 1 e 110 e 110 e 110 ps t skew output-to-output same part skew note 1 e 50 e 50 e 50 ps t jitter cycle-to-cycle jitter e 1 e 1 e 1 ps f max maximum output frequency functional to 1.5 ghz; timing specifications apply to 1.0 ghz e 1500 e 1500 e 1500 mhz t r /t f output rise/fall time at 20% to 80% all outputs terminated 50 w to v cc 2.0 v 100 300 100 300 100 300 ps note: 1. for operation with 2.5 v supply, the output termination is 50 w to v ee . for operation with 3.3 v supply, the output termination is 50 w to v cc 2 v.
philips semiconductors product data pck111 low voltage 1:10 differential ecl/pecl/hstl clock driver 2004 apr 23 6 lqfp32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm sot358-1
philips semiconductors product data pck111 low voltage 1:10 differential ecl/pecl/hstl clock driver 2004 apr 23 7 hvqfn32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm sot617-1
philips semiconductors product data pck111 low voltage 1:10 differential ecl/pecl/hstl clock driver 2004 apr 23 8 revision history rev date description _5 20040423 product data (9397 750 13082). supersedes data of 2003 dec 03 (9397 750 12451). modifications: ? add part type pck111bs, hvqfn32 package option (sot617-1). _4 20031203 product data (9397 750 12451); ecn 853-2281 01-a14515 dated 14 november 2003. supersedes data of 13 december 2002 (9397 750 10865). _3 20021213 product data (9397 750 10865); ecn 853-2281 29225 of 22 november 2002. _2 20020215 product data (9397 750 09465); ecn 853-2281 27735 of 15 february 2002.
philips semiconductors product data pck111 low voltage 1:10 differential ecl/pecl/hstl clock driver 2004 apr 23 9 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support e these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes in the productseincluding circuits, standard cells, and/or softwaree described or contained herein in order to improve design and/or performance. when the product is in full production (status `production') , relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2004 all rights reserved. printed in u.s.a. date of release: 04-04 document order number: 9397 750 13082 philips semiconductors data sheet status [1] objective data preliminary data product data product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii
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